1. Field of the Invention
The present invention relates to a memory control device for controlling writing and reading of data to a memory of a data storage device.
2. Description of the Prior Art
A great deal of data has been increasingly processed in accordance with the recent progress of informationized society, and recording and reproducing of the data has accordingly become more and more important. This forms the background of a strong demand for higher sophisticated recording and reproducing technique. Moreover, as the cost of semiconductor memories has been reduced because of the remarkable advancement of the technique, a high-speed semiconductor memory with large capacity has been often used as a recording medium of data.
FIG. 4 shows an example of a data recording/reproducing system using a semiconductor memory (referred to as a RAM hereinafter) as a data recording medium. Numerals 31-33 designate respectively a RAM, an arbiter and a memory control device. For example, when a READ demand is input to the arbiter 32 while RAM 31 is in writing data, it instructs the memory control device 33 to stop generation of a reading start signal RST until RAM 31 finishes writing and then to generate a reading start signal RST. On the contrary, if a WRITE demand is input thereto while RAM 31 is in reading out data, instructs the memory control device 33 to stop generation of a writing start signal WST until RAM. 31 finishes reading and to generate a writing start signal WST thereafter. Therefore, the memory control device 33 generates a signal to control RAM 31 based on the output result of the arbiter 32.
An example of the above memory control device 33 is shown in FIG. 5. The memory control device 33 consists of synchronous delay circuits 41 and 43 which are synchronized with writing and reading clock signals WCLK and RCLK and RS flip-flop circuits (referred to as an RS.FF hereinafter) 42 and 44. The writing start signal WST is connected to an input of the synchronous delay circuit 41 and a set input (referred to as an S input hereinafter) of RS.FF 42. On the other hand, an output of the synchronous delay circuit 41 is connected to a reset input (referred to as an R input hereinafter) of RS.FF 42. Further, the reading start signal RST is connected to an input of the other synchronous delay circuit 43 and an S input of RS.FF 44, while an output of the synchronous delay circuit 43 is connected to an R input of RS.FF 44.
The fundamental operation of the memory control device 33 will be explained with reference to FIG. 6.
When a WRITE demand signal generated by frequency-dividing writing clocks WCLKs is input to the arbiter 32, it generates a writing start signal WST in response thereto. This signal WST is input to the synchronous delay circuit 41 and to the S input of the RS.FF 42.
Since the S and R inputs of RS.FF 42 become "H" and "L" at that timing, the Q output of the same, i.e. the writes control signal WRT is turned "H" and, thereby, RAM 31 write into WRITE data. The synchronous delay circuit 41 delays the write start signal WST by a predetermined number of the writing clocks WCLKs and, thereafter, outputs a WRITE reset signal WRS to the R-input of RS.FF 42 to reset the same. Namely, RAM 31 is able to perform data writing for a delay time by the synchronous delay circuit 41.
Similarly, when a READ start signal WST is input to the S input of the RS.FF 44, the same outputs a READ control signal RED to enable RAM 31 to perform data reading and a READ reset signal RRS delayed by the synchronous delay circuit 43 is input to the R input of RS.FF 44 to reset the same.
In the manner as described above, when the number of delay clocks corresponding to the time necessary for the operation of RAM 31 is set in each of the synchronous delay circuits 42 and 44, it becomes possible to generate the writing control signal WRT or reading control signal RED to RAM 31 without competition with each other.
In the above arrangement of the memory control device, if the writing clock WCLK input to the synchronous delay circuit 41 has the same frequency as the reading clock RCLK input to the synchronous delay circuit 43, no particular problem is noticed.
However, a problem occurs when the writing clock WCLK is stopped. As shown in FIG. 6, when the writing start signal WST is "H", the writing control signal WRT becomes "H', so that data is written into RAM 31. If the writing clock WCLK alone is stopped in this state, the writing control signal WRT is retained "H", thereby causing RAM 31 to keep the writing condition. As a result, RAM 31 cannot read even if the reading clock RCLK is input. Likewise, while RAM 31 is in the reading state, if the reading clock RCLK is stopped without stopping the writing clock WCLK, RAM 31 cannot write. Also, in the case where the frequency of either the writing clock WCLK or reading clock RCLK is lowered, it brings about the same trouble as above.
In addition, if the frequency of the writing clock WCLK or reading clock RCLK is raised, the writing time or reading time to RAM 31 becomes insufficient thereby to cause an erroneous operation or a destruction of data.
As such, the memory control device 33 in the structure described above is not applicable to a system wherein either one or both of the writing clock WCLK and reading clock RCLK change its frequency, or a system wherein the writing clock WCLK or reading clock RCLK is stopped. In a system using the memory control device 33 of the above-described structure as well, it is impossible to change the frequency of either or both of the writing clock WCLK and reading clock RCLK, or to stop the writing clock WCLK or reading clock RCLK.